This invention relates generally to fault checking, and more particularly to fault checking of slave devices.
It is known to have master device control several slave devices. This may be done by the use of buses. In such a case, each slave device will have a unique address associated with it. A poll address bus is used to address each slave device in turn, and a poll mode bus is used to send control signals to the addressed slave device to elicit a particular response.
For example, the poll address bus may have seven lines which means that up to 128 slave devices may be involved. One test that is desirable to be able to perform is to test for the presence or absence of a slave device; another is to test for the operational status (i.e. operating or not operating) of a slave device that is present.
The test may be accomplished by using two bits to reply to the test. For example, the logic bits 11 returned by the slave device may indicate that the slave device is present and operational while the response 00 may indicate that the device is present but not operational. However, a fault may exist on the line drivers, causing the drivers to be stuck in the logic 1 position. Using known techniques this is difficult, if not imposible, to detect.